स्वदेशी Microprocessor Challenge - Innovate Solutions for #आत्मनिर्भर भारत

Background of स्वदेशी Microprocessor Challenge

Under #AatmaNirbharBharat Abhiyan, there is a growing need for Swadeshi Compute Hardware, that shall be part of every Smart Device deployed in different domains, including Electronics for public utility services such as Surveillance, Transportation, Environmental condition monitoring, to commodity appliances like smart fans/ locks/ washing machines. In addition, with growing penetration of smart electronics in strategic areas including Space, Defence and Nuclear energy, the need for Swadeshi Compute Hardware is crucial. It is not just the cost or embargo that drives this need, but also the dependence on external vendors, long term sustenance, quick enhancements to suit the ever-growing requirements, and most-importantly Security, which drives #AatmaNirbharta in Hardware domain, as the only option.

Under Microprocessor Development Programme spearheaded by MeitY at C-DAC, IIT Madras and IIT Bombay, not only the family of industry-grade Microprocessors has been designed from the scratch but also the compute ecosystem around them has been evolved as a step towards meeting India's future requirements.

Scope of स्वदेशी Microprocessor Challenge

To provide further impetus to the strong ecosystem of start-ups, innovators & researchers in the country, MeitY announces Swadeshi Microprocessor Challenge made available by IIT Madras (शक्ति processors) and C-DAC (वेगा processors), powered by FPGA Boards of XILINX which is supported by CoreEL Technologies, to promote a culture of innovation and entrepreneurship by taking up complex designs in the country and innovate frugal solutions around home-grown processor ecosystem, catering to both global and domestic requirements.The incubation support to the winning teams will be provided by an Incubator located at their geographical proximity coordinated by Maker Village.

Give your ideas a jump-start by sculpting your innovation with Technical support, Business mentorship augmented with Hardware, Software and funding support of total Rs. 4.30 Crore from MeitY to applicants at various stages of the Challenge as following.:

ELIGIBILITY CRITERIA

  1. All the participants must be Indian Nationals and should make use of one of the Microprocessors & associated ecosystem (शक्ति processors by IIT Madras or वेगा processors by C-DAC). While one of these Microprocessors & associated ecosystem (शक्ति processors by IIT Madras or वेगा processors by C-DAC) ported on Xilinx FPGA Boards ( Arty A7-100T or Arty A7-35T) will be readily made available to the participants by the Challenge Organizers at no cost, the applicants also have the option to participate by way of porting these Microprocessors & associated ecosystem by themselves on other FPGA Boards of their choice, from their own expenses.
  2. The contest is open to the following: –
    • All Indian students pursuing undergraduate, postgraduate & Doctoral degrees in Engineering discipline with Indian Colleges and Universities. Teams of not more than 5 students and 2 faculty members.
    • Start-up or,
    • Others, for those who are neither student nor Start-up.
  3. If Applicant is not yet registered as Start-up, they are still allowed to submit ideas, but are required to be registered as private limited company (as defined in the Companies Act, 2013) or registered as a partnership firm (registered under section 59 of the Partnership Act, 1932) or a limited liability partnership (under the Limited Liability Partnership Act, 2008) in India (as per definition available in the latest notification of DIPP at http://startupindia.gov.in) before 31st January 2021.
  4. An entity shall be considered as 'start-up' per definition of startup as notified by DPIIT vide order no G.S.R. 127(E) dated 19th February 2019:
    • Upto a period of ten years from the date of incorporation/ registration, if it is incorporated as a private limited company (as defined in the Companies Act, 2013) or registered as a partnership firm (registered under section 59 of the Partnership Act, 1932) or a limited liability partnership (under the Limited Liability Partnership Act, 2008) in India.
    • Turnover of the entity for any of the financial years since incorporation/ registration has not exceeded one hundred crore rupees.
    • Entity is working towards innovation, development or improvement of products or processes or services, or if it is a scalable business model with a high potential of employment generation or wealth creation. Provided that an entity formed by splitting up or reconstruction of an existing business shall not be considered a 'Startup'. Innovative Security Products being developed should not have violated/ breached/ copied any product already launched and/or copyrighted or patented.
    • For the product to be developed as part of the Challenge, if any IPR/Patent is being used, contesting entity must possess the legitimate rights to use the IPR/Patents.
    • The product to be developed for the Challenge should be designed and developed in India.
    • Any group of individuals, which is not registered as startup and wants to participate in the Challenge may participate with the condition that the group must register the entity by 31st January 2021 and submit the copy of registration to organizing committee failing which submitted proposal will not be considered further.

Contest Structure

The Challenge is divided into 4 Stages:

#

Stage

Timelines

1

Registration

18th August – 30th September 2020

2

Quarter Finals

01st October- 25th November 2020

3

Semi Finals

15th January – 31st March 2021

4

Finals

15th April – 30th June 2021

1. Registration

All the participating teams meeting the Eligibility Criteria are expected to register on or before 30th September 2020 at MyGov Portal here. Teams completing the registration process will enter into the Quarter Finals Phase.

2. Quarter Finals

All Quarter Finalists to go through the following steps:

  1. A). Pre-Screening Stage
    • Participating students to get approval from Faculty Mentor(s) from their respective College(s) as applicable.
    • Understand the technical details by going through the Tutorials (for Processor SDK, FPGA Boards, demo applications etc.) made av­ailable for शक्ति processors by IIT Madras or वेगा processors by C-DAC.
    • Submit the tentative Abstract of the proposal by 25th October 2020 within 2000 words and solving a Quiz to ensure that participant has fair understanding.
  2. B). Ideate Stage

    Submit the detailed Proposal by 25th November 2020.

The submissions will be reviewed by a panel of domain experts against 2 categories – Business Potential and Technical Innovation. The announcement for the 100 Teams to be shortlisted for the Semi Finals Stage will be made by 10th January 2021.


3. Semi Finals

All 100 Semi finalists to go through the following steps:

  1. A). Minimum Viable Prototype (MVP) Stage
    • Each Semi Finalist Team will be provided with the- (a) Cash Prize of Rs. 25,000/-, (b) access to Indigenous Processor Ecosystem and (c) Xilinx Board to develop the MVP.
    • The monthly progress to be submitted along with following- Progress Report including deviations, if any, and Video demonstration of MVP & Business Plan.
  2. B). Proof-of-Concept (POC) Stage
    • Further Rs. 75,000/- may be provided to those Semi Finalists during the 1st review, who – (a) either demonstrate POC/ substantial progress or, (b) require additional COTS to demonstrate a POC.
    • All Semi Finalists to demonstrate the POC/ MVP on 31st March 2021.

The POC/ MVP will be reviewed by a panel of domain experts against 2 categories – Business Potential and Technical Innovation. The announcement for the 25 Teams to be selected for the Finals will be made by 15th April 2021.


4. Finals

All 25 Finalists to go through the following steps:

    • Each Finalist will be provided with the Cash Prize of Rs. 4.00 Lakh to develop the Hardware Prototype.
    • The monthly progress to be submitted along with following- Progress Report including deviations, if any, and Video demonstration of Hw Prototype & Business Plan.
    • All Finalists will be invited to demonstrate their Hw Prototype in the Final Evaluation event.

5. Winners

Top 10 Teams winning in the Final Stage will be announced in July 2021 for the following awards & support towards incubating the Start-up at identified Incubation Centre-

    • Rs. 35.00 Lakh to the Winning Team,
    • Rs. 30.00 Lakh to 1st Runner-up Team,
    • Rs. 25.00 Lakh to 2nd Runner-up Team
    • Total Rs. 1.40 Crore to 7 other Teams.

Important Dates

Stage

Intermediate Stages

Timelines

Registration

 

18th August – 30th September 2020

Quarter Finals

 

01st October – 25th November 2020

Pre-Screening Stage: Abstract submission and solving a Quiz by 25th October 2020.

Ideate Stage: Detailed proposal submission by 25th November 2020.

Quarter Finals Phase Results

 

10th January 2021

Shipment of Xilinx FPGA Board ported with Swadeshi Processor to Semi Finalists

 

10th January – 15th January 2021

Semi Finals

 

15th January - 31st March 2021

Preliminary Document Report submission for review by 31st January 2021

Progress Report submission by 28th February 2021

POC/ MVP submission by 31st March 2021

Semi Finals Results

 

15th April 2021

Finals

 

15th April – 30th June 2021

Progress Report submission by 31st May 2021

Final Results

 

July 2021

Outcomes and Awards

Outcomes

REWARDS AND RECOGNITION : Win lucrative prize money at various stages of the Challenge.

FAST TRACK YOUR FUTURE : A platform to innovate and demonstrate capabilities.

VISIBILITY : A high viewership platform provides you with an opportunity to showcase and promote your innovation.

BE MENTORED BY THE BEST : Opportunity to gain mentorship and guidance under the best VLSI & Electronics System Design Experts in the country.

EXPAND YOUR REACH : Opportunity to meet peers, domain experts and other stakeholders.


Awards:

Processors

Under Microprocessor Development Programme initiated by MeitY, a family of 32-bit/ 64-bit Microprocessor has been designed from the scratch using Open Source ISA (Instruction Set Architecture), as a step towards meeting India’s future requirements of strategic/ commercial/ Industrial sector. Out of these, following processors along with the associated ecosystem ported on Xilinx Boards are made available to the participants of this Challenge:


शक्ति Processor Ecosystem

The SHAKTI Processor Program, a first-of-its-kind initiative in the country, started as an academic initiative back in 2014 at IIT-Madras, with the sole aim of building an open source processor ecosystem which would not only be of industrial grade quality but will also push India at the frontier of microprocessor research.

Under the Microprocessor Development Programme of MeitY, IIT Madras has designed and developed a family of industry-grade 32-bit and 64-bit Microprocessors from the ground up as a step toward meeting India's future requirements of strategic/ commercial/ Industrial sector. These processors have been fabricated using Intel's 22nm Technology at Oregon (USA) and also in 180nm at the Indian foundry SCL, Mohali. The processors hold the potential to serve more than 80% of India's strategic computing needs. With continued support from MeitY, today the SHAKTI initiative (apart from micro-processors) offers: complete software stack, FPGA prototypes, interconnect fabrics, accelerators, device IPs, verification suites, and much more all for free under permissive open source licenses.

As part of the Swadeshi Microprocessor Challenge, IIT Madras will make available three FPGA proven SoCs based on SHAKTI processors for participants to build novel applications:

  • Pinaka (E32-A35) and Parashu (E32-A100): These SoCs employ a 3 stage, 32-bit in-order E-class processor core. Pinaka is the E class based SoC on the Artix7-35T FPGA board and Parashu is the E class based SoC on the Artix7-100T FPGA Board. The E-class processor cores are designed for low power/area constraints and suitable for applications like smart-cards, IoT, Embedded platforms, motor-controls and robotic platforms, etc. The SoCs include a wide variety of devices like: PWMs, SPIs, UARTs, I2Cs, GPIOs, XADC, Timers, PLICs (Programmable Interrupt Controllers) and includes Physical Memory Protection (PMP). Both the SoCs have Pin Mux enabled and Arduino compatible. Parashu includes access to a high speed DDR memory and Ethernet Lite as well.
  • Vajra (C64-A100): : This particular SoC employs a 64-bit, linux capable, 6-stage, in-order C-class processor core on the Artix7-100T FPGA Board. The C-class processor core includes many performance rich features like branch predictors, caches, operand bypass, etc., thereby delivering substantial performance at minimal area/power overheads. Vajra includes all the devices of Parashu and can be useful for high performance applications like networking, gateways, storage, etc.

Each of the above SoC are accompanied by a full-stack SDK and IDE to ease development of applications. For more details on SHAKTI Processor Ecosystem, please visit here


वेगा Processor Ecosystem

Under the Microprocessor Development Programme of MeitY, C-DAC has successfully completed the design, development and validation of a series of 32-bit /64-bit Single and Multi-core superscalar Out-of-Order high performance processors named 'VEGA', based on the open source RISC-V Instruction Set Architecture (ISA) with Multilevel Caches, Memory Management Unit and Coherent Interconnect. C-DAC has also integrated a wide range of in-house developed Silicon proven System and Peripheral IPs and has successfully ported the SoCs on FPGA boards, booted Linux/ FreeRTOS, run various applications and verified the performance with standard benchmarks. The complete software ecosystem comprising of the Board Support Packages, SDK with integrated tool chain, IDE plug-ins and Debugger for development, testing and debugging is also available.

As part of the Swadeshi Microprocessor Challenge, C-DAC will make available two VEGA microprocessor ecosystem variants for participants to choose based on their requirements and targeted application:

  • VEGA ET1031, a 32-bit high performance microcontroller class processor comprising of a 3-stage in-order RISC-V based core. This processor design is compact and efficient and is targeted for applications like sensor fusion, smart meters, small IoT devices, wearable devices, electronic toys, etc. The peripherals available in VEGA ET1031 processor based SoC are GPIO, Interrupt Controller, Timers, RAM, SPI, UART, I2C, PWM and ADC. This SoC is targeted for Arty A7-35T FPGA board.
  • VEGA AS1061, a 64-bit processor with a 6-stage in-order pipeline optimized for high performance. This processor comprises of an efficient branch predictor and Instruction & Data caches and is targeted for applications like IoT devices, motor control, wearable devices, high-performance embedded, consumer electronics and industrial automation. The peripherals available in this VEGA AS1061 processor based SoC are GPIO, Interrupt Controller, Timers, DDR3 RAM, SPI, UART, I2C PWM, ADC and 10/100 Ethernet. This SoC is targeted for Arty A7-100T FPGA board.

For more details on VEGA Processor Ecosystem, please visit here

Sample Applications

The family of processors & associated ecosystem with varied capabilities and Xilinx development Board are provided free of cost under the Challenge. The students are expected to choose the appropriate processor based on the application to be targeted by them and augment it with other COTS (Commercial-off-the-shelf) components comprising Boards with additional sensors, devices, instruments, to build a Working Prototype of their solution. Some of the indicative areas, not limited to the following:

  1. IoT Based Weather Reporting System
  2. IoT Based Alarm Clock
  3. IoT Based Air Pollution Monitoring System
  4. IoT Based Health Monitoring System
  5. IoT Based Smart Water Irrigation System
  6. IoT Based Traffic Management System
  7. IoT Based Baby Monitoring
  8. IoT Based Garbage Monitoring System
  9. IoT Based Street Light Monitoring System
  10. IoT Based Early Flood Detection and Avoidance
  11. IoT Based Wheelchair Fall Detection
  12. Touch-Based Home Automation System
  13. Facial Recognition Door 
  14. Night Patrolling Robot
  15. Smart Parking System
  16. Gas Pipe Leakage Detector
  17. Smart Baggage Tracker
  18. Liquid Level Monitoring
  19. Smart Garage Door
  20. Smart Anti-theft System
  21. Drones
  22. Robotic applications
  23. Smart city applications
  24. Solutions for Environment
  25. Smart systems for medical applications

More to be added soon

FAQs

Q. Do I have to register for the contest?

A. Yes, you must register for the Challenge by following the Application Process here.

Q Who is eligible to participate in the contest?

A. The details are provided in the Eligibility Criteria here

Q. What will be the process after Registration?

A. Each Team meeting the eligibility criteria will be provided with the Registration ID and will enter into the Quarter Finals. The details of subsequent steps will be updated by 30th September 2020 here

Q. Can a team submit more than one application?

A. No. Each Team can submit only one application.

Q. Is there a deadline for registration?

A. Yes. The deadline for registration is 23:59 (IST) on 30th September 2020

Q. How many students can form a team?

A. The details are provided in the Eligibility Criteria here

Q. Who can be a faculty mentor?

A. Any faculty member from the Indian colleges/ universities is eligible to be a faculty mentor.

Q. Can students from different departments within the same college form a team?

A Yes, students from different departments within a college can form a team.

Q. Can students from different colleges form a team?

A. The students from different colleges can form a Team.

Q. Can individuals other than students participate in the Challenge?

A. Yes. Any group of individuals, who are not student and also not registered as Start-up, may participate with the condition that the group must get registered by 31st January 2021 as per the details given in the Eligibility Criteria.

Q. Will the hardware/ software tools and kits be provided by the Organizing Agencies or will I have to manage it myself?

A. Access to Indigenous Processor Ecosystem and Xilinx Board are made available to the participants during SemiFinals at nocost.

Q. Where can I find the details about the processors?

A. The details about SHAKTI processor by IIT Madras is available here and VEGA processor by C-DAC is available here

Q. I have some technical questions regarding FPGA kits/ drivers/ tools. Who should I contact?

A. You may Contact Us at here

Q. Can I use Microprocessor IP or FPGA Board of my choice ?

All the participants should make use of one of the Microprocessors & associated ecosystem (शक्ति processors by IIT Madras or वेगा processors by C-DAC). While one of these Microprocessors & associated ecosystem (शक्ति processors by IIT Madras or वेगा processors by C-DAC) ported on Xilinx FPGA Boards ( Arty A7-100T or Arty A7-35T) will be readily made available to the participants by the Challenge Organizers at no cost, the applicants also have the option to participate by way of porting these Microprocessors & associated ecosystem by themselves on other FPGA Boards of their choice, at their own expense.

Contact us

  1. For general queries related to the Challenge, please contact swadeshi[dot]processor[at]meity[dot]gov[dot]in or post at discussion forum available here
  2. For queries related to SHAKTI processor Ecosystem, please post at discussion forum available here
  3. For queries related to VEGA processor Ecosystem, please post at discussion forum available here

What's New

  1. The Registration for the Swadeshi Microprocessor Challenge is now closed. All successfully registered applicants are part of the Quarter Final Stage.
  2. The deadline for submitting the Proforma in Pre-screening Stage of the Quarter Finals is 25th October 2020. For submitting the Proforma and details on further steps of the Quarter Final Stage, please visit here
  3. The Registration is now open for the 2-week Instructor-led/ self-paced Online Training being organized by NIELIT Calicut on various technical aspects of the Swadeshi Microprocessor Challenge, commencing from 05th October 2020. For Registration, please visit here
  4. The recorded version of Interactive Webinar on the Swadeshi Microprocessor Challenge held on 21st September 2020 is available here

Submission Closed